1. Field of the Invention
The present invention relates to a semiconductor chip package, and more particularly to a bottom lead semiconductor chip stack package for combining a pair of separate chips into a single package while obviating a wire bonding process and facilitating the fabrication thereof.
2. Description of the Prior Art
In a SOJ (small outline J-lead) semiconductor chip package serving as one of a variety of semiconductor packages, a semiconductor chip is mounted by an insulating tape or a paste on a paddle of a lead frame thereof. A plurality of pads in the chip are electrically connected by metallic wires to corresponding inner leads of the lead frame, followed by a resin molding of the structure. The outer leads extending from the package body molded structure are respectively formed in the "J" type configuration, thereby completing the chip package.
The thus composed conventional SOJ semiconductor chip package must pass an electrical characteristic test for its industrial application, whereby the package is mounted on or in a setting substrate for implementing its required operation, such as in a memory module.
However, the above-described conventional chip package has the disadvantage that the increased package area occupied on the substrate due to the outer leads extending from each side of the package results in a decrease in the yield due to the bending of the outer leads.
U.S. Pat. No. 5,428,248 granted to the present assignee on Jun. 27, 1995 was directed to overcoming the above disadvantage, and the patented chip package is called a BLP (bottom lead semiconductor package) which is now in mass production.
Referring to FIG. 1, the conventional bottom lead semiconductor package includes: a lead frame 2 having a plurality of substrate connection leads 2a each of which is connected to a substrate (not shown) and a plurality of chip connection leads 2b, upwardly extending from the substrate connection lead 2a. A semiconductor chip 1 is mounted by an adhesive 3 on each of the substrate connection leads 2a and a plurality of metallic wires 4 are provided for electrically connecting each of chip pads 1a to a corresponding one of the chip connecting leads 2b of the lead frame 2. The components including the wires 4, the chip 1, the lead frame 2 and the leads 2a, 2b are molded into a component by a molding resin 5 to form a package body which exposes the lower surface of each of the substrate connection leads 2a.
The thus composed conventional bottom lead semiconductor package reduces the area occupied on the substrate and prevents the outer leads from being damaged.
However, the chip pads 1a are electrically connected to the corresponding chip connection leads 2b by metallic wires 4 so that there is a limitation in making the chip package thinner because of the increase in height of the package body for accommodating the metallic wires.
Furthermore, because only a single chip is mounted in the chip package, multi-layer packages are difficult to produce, thereby restraining large integration.
Still further, the lead connection state is difficult to test.